AMD attacks the rack with Helios systems that rival Nvidia's

AMD attacks the rack with Helios systems that rival Nvidia's Spec for spec, the House of Zen's first rack-scale AI compute platform is bigger and faster than Nvidia's Vera Rubin by nearly every metric, but that's only on paper Could Nvidia's days of datacenter dominance be threatened? With the launch of Helios, AMD’s first true rack-scale AI platform, the House of Zen is done playing catch up. The company claims the rack system is powered by the fastest AI accelerators on the market. And, at least on paper, the 72-GPU system is not only bigger and faster by nearly every metric than Nvidia’s existing Blackwell-based rack systems but than Vera Rubin as well, and that includes the rack. Measuring in at 1.2 meters wide and 44OUs high, the OCP Open Rack Wide form factor is nearly twice the size of Nvidia's NVL72, and AMD has clearly put the extra space to good use. REG AD Compared to Vera Rubin, Helios boasts 50 percent more HBM4 and scale out bandwidth and between 15 and 25 percent higher performance for AI training. REG AD Vera Rubin’s adaptive compression tech will supposedly give it a 25 percent lead over Helios at FP4, but, as we understand it, that’s only for inference workloads. For applications that can’t, Helios offers 15 percent higher peak FP4 FLOPS. To be clear, it’s not the first time we’ve seen AMD pull ahead on memory or FLOPS. The difference is those products usually launched a year after Nvidia’s equivalent part. Helios launches right in time with Nvidia’s Vera Rubin platform. AMD estimates Helios' higher peak performance will give it a 30 percent performance per dollar lead over the competition. The belly of the beast Helios' performance gains are rooted in an all-new GPU built on AMD’s 5th-gen CDNA compute architecture. Much like the rack it powers, the Instinct MI455X is massive, though the chip is underselling it a bit. Just like the MI300 series, AMD’s latest datacenter GPU is a silicon sandwich that stitches together I/O, compute, and memory in a single package. Including memory, MI455X features 24 chiplets using a combination of 2.5D and 3D packaging technologies. The chip’s eight compute dies are fabbed on TSMC’s bleeding edge 2nm process tech, which are stacked atop a pair of 3nm fabric and cache dies (FCDs). The FCDs are an interesting twist on the formula. They function as a cache heavy interposer with 96 MB of L2 cache each and the memory controllers for the chip’s 12, 36 GB HBM4 stacks. Unlike past Instinct accelerators in which the I/O die was located under the compute, the MI455X breaks these out into two new dies — also fabbed on TSMC’s 3 nm — which are responsible for chip-to-chip communication. REG AD One benefit to this architecture is that the chip can be made to function as one big GPU or two smaller ones depending on which NUMA configuration you opt for. The chip also supports spatial partitioning into up to eight virtual GPUs. Under the hood, AMD’s CDNA architecture brings some notable improvements over the last…